Analysis and Improvement of Error-Tolerant in the Digital Systems by Using Static Segmentation of Multifunctional Multipliers

Abstract

The demand for energy-efficient and high-performance computing systems is continuously increasing due to the rapid growth of ubiquitous computing devices and the large volume of data that needs to be processed. Edge computing, for instance, requires fast data analysis near the data acquisition points to reduce response time and save bandwidth. At the same time, these systems must operate under strict power constraints, especially in battery powered embedded and mobile devices. The need for low-power and high-speed circuits has led to the development of new design paradigms. Approximate computing has emerged as a promising technique to achieve these objectives by sacrificing arithmetic accuracy in computation results. This approach is suitable for applications such as multimedia processing and machine learning, where a small loss in accuracy is acceptable. In recent years, approximate arithmetic circuits, particularly adders and multipliers, have been extensively studied because they are among the most power-consuming digital components. Several approaches have been proposed to design highly efficient approximate multipliers. In logarithmic multipliers, the product is obtained by adding approximate logarithms of the operands and then computing the antilogarithm of the result. Recursive multipliers use small elementary approximate multiplier blocks, typically of size 2×2 or 4×4, which are combined hierarchically. Multipliers based on approximate compressors or counters are designed to efficiently sum partial products. Truncated multipliers eliminate some of the least significant partial products, and the resulting truncation error is reduced using suitable correction functions. Genetic optimization algorithms have also been applied to explore the design space of approximate multipliers. In addition, approximate Booth multipliers have been proposed by various researchers. Customized approximate multipliers for efficient implementation of multiply accumulate (MAC) units have also been developed. These designs exploit error mitigation and correction techniques and combine the multiplier and adder into a unified approximate structure. An important class of approximate multipliers, known as segmented multipliers, extracts a set of m contiguous bits (an m-bit segment) from each of the two n-bit operands. These segments are multiplied using an internal m×m multiplier, and the resulting 2m-bit product is shifted appropriately to produce the final 2n-bit output. In this work, we investigate approximate multipliers based on static segmentation. In these circuits, a fixed set of m contiguous bits is extracted from each of the two n-bit operands. The extracted segments are applied to a small m×m internal multiplier, and its output is properly shifted to generate the approximate result. Both signed and unsigned multipliers are analyzed, and for unsigned multipliers, a new segmentation technique is proposed. We also introduce simple and effective correction techniques that significantly reduce approximation errors with minimal hardware overhead. A detailed comparison with previously proposed approximate multipliers is performed using a 28 nm technology implementation. The results show that static segmented multipliers with the proposed correction techniques lie on or close to the Pareto-optimal frontier for both power versus normalized mean error distance (NMED) and power versus mean relative error distance (MRED) trade-off curves. Therefore, these multipliers are promising candidates for applications where a certain level of error is acceptable. This conclusion is further supported by experimental results obtained from image processing and image classification applications.