DESIGN AND SIMULATION OF HARDWARE-BASED ETHERNET MAC FIREWALL FOR INDUSTRIAL NETWORKS

Abstract

Industrial networks such as SCADA and Industrial Control Systems (ICS) require secure and reliable communication while maintaining strict timing constraints. With the increasing use of Ethernet-based communication in these systems, the risk of cyber threats such as unauthorized access and malicious data transmission has significantly increased. Traditional software-based firewalls are not well-suited for such environments, as they introduce variable delays that can affect real-time operations. This project presents the design and simulation of an Ethernet MAC firewall intended for industrial networks. The proposed system integrates packet filtering functionality with the Ethernet Media Access Control (MAC) layer to enable real-time inspection and control of network traffic. The design is developed using Verilog Hardware Description Language (HDL) and verified through simulation, ensuring that the system operates correctly under different conditions. The firewall inspects essential packet parameters such as source and destination addresses and applies predefined rules to determine whether a packet should be allowed or blocked. By performing these operations at the hardware level, the system achieves fast and predictable performance, making it suitable for time-sensitive applications. The results obtained from simulation demonstrate that the proposed design can effectively filter network traffic with minimal delay. Although the system is not physically implemented on hardware, it is fully synthesizable and can be deployed on FPGA platforms in future work. This approach provides a reliable and efficient solution for enhancing security in industrial communication networks.