Design and analysis of bootstrap integrated 6T SRAM in 90nm technology

Abstract

The study focuses on a comparative analysis of a traditional CMOS-based 6T SRAM cell and a bootstrap-assisted SRAM cell, both designed using 90nm technology. Bootstrapping is a technique used to improve the driving strength of digital circuits. This circuit allows node voltages to rise above VDD and fall below ground, enabling efficient operation even at low supply voltages. The SRAM cells are not compatible with contemporary low-power applications due to their reduced stability and write performance at low voltages. In the proposed circuit, the input voltage given to the SRAM circuit is increased above VDD using a bootstrapped circuit, thus improving the performance of the overall circuit. Read delay, write delay, SNM, leakage current, power dissipation, and PDP are used to assess the performance of both circuits. To evaluate the designs’ suitability for low-power and high-speed memory applications, Cadence Virtuoso is used to develop and simulate them using 90 nm CMOS technology. The comparative results indicate that the bootstrap-assisted SRAM circuit exhibits improved read and write stability compared to the conventional design. The findings further demonstrate that the SRAM cell can operate reliably at lower supply voltages when the bootstrap circuit is incorporated.