HARDWARE IMPLEMENTATION OF CANNY EDGE DETECTION ALGORITHM USING VERILOG HDL

Abstract

Edge detection is a key operation in computer vision, image processing, and embedded intelligent systems. Traditional software implementations of the Canny algorithm suffer from high computational latency and lack the performance required for real-time applications. This paper presents a full custom hardware architecture for the Canny edge detection algorithm, implemented using Verilog HDL and optimized for FPGA platforms. The proposed design includes Gaussian smoothing, Sobel gradient computation, CORDIC-based magnitude and direction calculation, non-maximum suppression, double thresholding, and edge tracking via hysteresis. A deep pipelined, resource-efficient architecture enables real-time processing of 512×512 grayscale images at 100 MHz, achieving 380 frames per second. Simulation and synthesis were performed using ModelSim, Matlab and Xilinx FPGA tools. The design achieves a speedup of 250× over software-based methods, demonstrating superior performance in throughput, latency, and power efficiency. The architecture requires 8432 LUTs, 12,567 FFs, and 48 BRAMs, outperforming previous hardware implementations in design balance and scalability.
Keywords: Canny Edge Detection, FPGA, Verilog HDL, Image Processing, Hardware Acceleration, Pipelined Architecture, CORDIC