Design Of Low-Cost And High-Accurate 8-Bit Logarithmic Floating-Point Arithmetic Circuits

Abstract

This thesis presents the design and implementation of a low-cost and high-accuracy 8-bit Logarithmic Floating-Point (LFP) arithmetic unit, intended for efficient computation in low-power and high-speed embedded systems. Conventional IEEE-754 floatingpoint units (FPUs) involve high hardware cost due to the need for normalization, rounding, and complex multiplier hardware. In contrast, the proposed LFP architecture performs operations in the logarithmic domain, replacing multiplication and division with addition and subtraction operations. The complete design is modelled in Verilog HDL and synthesised using the Xilinx Vivado tool. Simulation results demonstrate up to 25% delay reduction and 20% area savings when compared to existing architectures. This work demonstrates that logarithmic arithmetic can significantly enhance computational efficiency without substantial accuracy loss, thereby making it highly suitable for next-generation IoT and DSP processors.