DESIGN AND ANALYSIS OF AES CRYPTOGRAPHIC CORE USING VERILOG HDL

Abstract

he Advanced Encryption Standard (AES) is a symmetric block cipher algorithm widely used for securing digital communication and data storage. This project focuses on the design and implementation of AES using Verilog HDL. The AES algorithm operates on 128-bit data blocks with variable key lengths of 128, 192, or 256 bits. The design includes the essential operations of Sub Bytes, Shift Rows, Mix Columns, and Add RoundKey, executed across multiple rounds depending on the key size. Verilog HDL is used to model the internal architecture at the Register Transfer Level (RTL) for improved modularity and synthesis efficiency. Functional verification is performed using simulation tools like Xilinx ISE to validate encryption and decryption processes. The proposed design achieves optimized speed, area, and power consumption, making it suitable for real-time security applications. The hardware-based AES design offers enhanced data protection for communication networks, IoT devices, and embedded systems. Overall, the work demonstrates that Verilog HDL provides a flexible and reliable platform for implementing cryptographic algorithms in modern digital security solutions.