LOW POWER ARITHMETIC LOGIC UNIT DESIGN FOR IOT APPLICATIONS

Abstract

The increasing adoption of Internet of Things (IoT) technologies necessitates energy-efficient and optimized processor architectures. A fundamental unit within these architectures is the Arithmetic Logic Unit (ALU), which plays a pivotal role in computational operations and overall system performance. This study introduces an enhanced ALU design incorporating a hybrid approach of clock gating and gray coding techniques, termed CGGC. By leveraging these methods, unnecessary switching activities are minimized, leading to lower power consumption and improved hardware efficiency. The design was developed using Verilog and validated on the Vivado 16 simulation platform. Experimental findings indicate an 18% reduction in Look-Up Table (LUT) utilization, demonstrating significant resource optimization for IoT-based applications. The proposed CGGC architecture ensures a synergy between computational efficiency and power conservation, making it a viable candidate for low-power embedded systems. Future research will focus on refining power optimization strategies and implementing the architecture on FPGA platforms for practical validation.