DESIGN AND ANALYSIS OF LOW-POWER, HIGHSPEEDERROR-TOLERANTADDERUSING GATEDIFFUSIONINPUTTECHNIQUE

Abstract

Instate-of-the-artVLSIcircuits,completelypreciseresultsarenotalwaysessential.Asaresult, engineershavebeguntodeveloperror-tolerantcircuitsthatprovidesatisfactoryperformancefor computing tasks. Building on this concept, the Error Tolerant Adder (ETA) emerges as a promisingsolution,offeringamethodforachievingexcellentpowerandspeedperformance.This paperpresentsa32- bitETAdesignedusingtheGateDiffusion Input(GDI)technique,amodern and efficient logic design style. The proposed design features an 11transistor (11T) GDI full adder,whichsignificantlyreducestheareaintermsoftransistorcountwhilealsoenhancingdelay andpowerperformance.Accordingtosimulationdata,theproposeddesignsurpassestheexisting designsintermsofthePowerandDelay.TheadoptionoftheGDItechniqueallowsforminimized power consumption and improved processing speed, making it a highly efficient choice for contemporary VLSI circuit design. This approach demonstrates how error-tolerant computing can be effectively implemented to meet the demanding requirements of modern electronic systems, where performance and energy efficiency are paramount. The need for low power portable devices has increased due to the expanding market for multimedia applications. High speed performance is also preferred at the same time. Designers have begun to compromise on accuracy in order to concurrently accomplish both of these objectives. Speed and power consumption have improved byimplementing this novel idea. The traditional CMOS logic style has been used to construct the ETA design. The hardware implementation of our suggested architecture uses the gate diffusion input (GDI) approach. A brand-new type of logic design known as GDI reduces the transistor count significantly. By adoptingthis technique, simplelogicoperations that call forfour, six, oreven twelvetransistors in typical CMOS logic style can be created with just two transistors. ThetoolsusedintheprojectareS-Edit,T-SpiceandW-Edit,whicharepopularsimulation tools used for simulating electronic circuits. The GDI technique is used to reduce power consumptionandincreasespeed.Theproposedadderiscomparedwithexistingaddersinterms of power consumption, speed, and error tolerance. The results show that the proposed adder achieves high-speed performance, low power consumption, and error tolerance. The proposed adder is suitable for various applications, including digital signal processing, arithmetic logic units, and low-power electronics. The hardware implementation of our suggested architecture uses the gate diffusion input (GDI) approach.Abrand-new type of logic design known as GDI reduces the transistor count significantly. By adopting this technique.