Advanced Design for Testability (DfT) Techniques for Low-Power andHigh-Performance VLSI Circuits: A Comprehensive Framework

Abstract

The exponential growth in Very Large Scale Integration (VLSI) circuit complexity, coupled with aggressive technology scaling below 7nm nodes, has introduced unprecedented challenges in circuit testing and validation. This research presents a novel framework for advanced Design for Testability (DfT) techniques specifically engineered for next-generation low-power, high-performance VLSI circuits. Our proposed methodology integrates intelligent scan chain optimization, advanced Built-In Self-Test (BIST) architectures, and power-aware testing strategies through a unified approach leveraging artificial intelligence and machine learning algorithms. Through comprehensive evaluation on industry-standard benchmark circuits, our approach demonstrates superior performance with fault coverage exceeding 98%, power reduction during test operations surpassing 20%, and area overhead maintained below 5%.