DESIGN AND FPGA IMPLEMENTATION OF HIGHPERFORMANCE 64-BIT HYBRID ADDER ARCHITECTURES FOR OPTIMIZED POWER-DELAY-AREA PERFORMANCE. int. J. Eng. Res. Sci. Tech. [Internet]. 2026 Jun. 13 [cited 2026 Aug. 16];22(2(1):2785-80. Available from: https://ijerst.org/index.php/ijerst/article/view/3455