DESIGN AND ANALYSIS OF HIGH SPEED WALLACE TREE MULTIPLIER USING PARALLEL PREFIX ADDRESS FOR VLSI CIRCUIT DESIGN. International Journal of Engineering Research and Science & Technology, [S. l.], v. 21, n. 2, p. 1681–1696, 2025. DOI: 10.62643/. Disponível em: https://ijerst.org/index.php/ijerst/article/view/922. Acesso em: 9 nov. 2026.