Efficient Clock Gating Techniques For Power Management In Domino Logic Using 16nm Technology. International Journal of Engineering Research and Science & Technology, [S. l.], v. 21, n. 2, p. 559–564, 2025. DOI: 10.62643/. Disponível em: https://ijerst.org/index.php/ijerst/article/view/745. Acesso em: 9 nov. 2026.