DESIGN OF 64-BIT SIGNED MAGNITUDE COMPARATOR USING FPGA FOR IOT APPLICATIONS. International Journal of Engineering Research and Science & Technology, [S. l.], v. 21, n. 1, p. 521–530, 2025. DOI: 10.62643/. Disponível em: https://ijerst.org/index.php/ijerst/article/view/591. Acesso em: 16 aug. 2026.