ADAPTIVE PRECISION-SCALABLE MULTIPLIER ARCHITECTURE FOR LOW-POWER, AREA-EFFICIENT, AND HIGH-PERFORMANCE VLSI APPLICATIONS. International Journal of Engineering Research and Science & Technology, [S. l.], v. 19, n. 4, p. 173–181, 2023. DOI: 10.62643/ijerst.2023.v19.n4.4596. Disponível em: https://ijerst.org/index.php/ijerst/article/view/4596. Acesso em: 27 oct. 2026.