HIGH SPEED AREA EFFICIENT VLSI ARCHITECTURE OF THREE OPERAND BINARY ADDER. International Journal of Engineering Research and Science & Technology, [S. l.], v. 20, n. 1, p. 47–55, 2024. Disponível em: https://ijerst.org/index.php/ijerst/article/view/205. Acesso em: 16 aug. 2026.