Error-Resilient Approximate Full-Adder Architectures for Low-Power Arithmetic: A Comparative Error and Power Analysis. International Journal of Engineering Research and Science & Technology, [S. l.], v. 22, n. 3, p. 560–567, 2026. DOI: 10.62643/. Disponível em: https://ijerst.org/index.php/ijerst/article/view/4093. Acesso em: 24 jul. 2026.