DESIGN OF LOW POWER AND AREA EFFICIENT OF BAUGH-WOOLEY MULTIPLIER

Abstract

The design of efficient digital multipliers plays a critical role in modern computing systems, especially in applications such as signal processing, image processing, and cryptography. This paper presents a design for a low-power and area-efficient Baugh-Wooley multiplier, which is a widely used algorithm for multiplying binary numbers. The proposed design focuses on reducing both the power consumption and the area of the multiplier while maintaining its accuracy and performance. By optimizing key components such as partial product generation, reduction stages, and carry propagation, the design achieves substantial power savings and area reduction compared to traditional multipliers. Furthermore, the integration of techniques like voltage scaling, clock gating, and efficient logic gates helps in minimizing power usage without compromising speed. The Baugh-Wooley multiplier’s inherent parallelism makes it suitable for high-speed applications, and with these optimizations, it is made more efficient for resource-constrained environments such as mobile devices and embedded systems. Simulation results demonstrate the effectiveness of the design, showing a significant reduction in both power and area while preserving the multiplier's functional correctness.