A LOW POWER AND HIGH-SPEED CONFIGURABLE ADDER FOR APPROXIMATE COMPUTING

Abstract

Approximate computing has emerged as a promising paradigm for error-tolerant applications, enabling trade-offs between computational accuracy, power efficiency, and performance. Addition, being a fundamental operation in many applications, is a key target for optimization in this domain. This work presents a novel low-power, high-speed, and accuracy-configurable adder tailored for approximate computing. The proposed design leverages a conventional carry look-ahead adder (CLA) architecture, incorporating a dynamic carry masking mechanism to enable runtime configurability of accuracy. Experimental evaluations on a 16-bit adder demonstrate significant improvements, in power consumption, with minimal area overhead. Compared to state-of-the-art approximate adders, the proposed design strikes an optimal balance between power, speed, and flexibility, showcasing its potential for efficient implementation in diverse approximate computing applications.